Integrated circuit (IC) design becomes more challenging as IC technologies continually progress towards smaller feature sizes, such as 32 nanometers, 28 nanometers, 20 nanometers, and below. For example, when fabricating IC devices, IC device performance is seriously influenced by lithography printability capability, which indicates how well a final wafer pattern formed on a wafer corresponds with a target pattern defined by an IC design layout. Various methods (such as immersion lithography, multiple patterning lithography, extreme ultraviolet (EUV) lithography, and charged particle beam lithography) have been introduced for enhancing lithography printability. In particular, charged particle beam lithography, which involves writing an IC pattern on a workpiece using a charged particle beam without a mask, can form IC features smaller than a resolution of light. However, scattering behavior of the charged particle beam as it scans the workpiece limits often results in final wafer patterns having poor image contrast. Accordingly, although existing lithography systems and lithography methods have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects